This invention relates to a blind adaptive decision feedback equalizer for high-speed serial communications, particularly in a high-speed serial interface of a programmable integrated circuit device.
It has become common to include embedded high-speed serial interfaces in programmable integrated circuit devices such as programmable logic devices (PLDs), programmable microcontrollers, etc. Higher data volumes demand high-speed, high-throughput data processing. Serial communication reduces the number of pins and parallel lines on a device, therefore, reduces the overall cost of the device and removes the problem of data skew in parallel lines.
In such interfaces, many different signalling schemes may be used, including binary, Non-Return to Zero (NRZ), multi-level Pulse Amplitude Modulation (e.g., 4-PAM), and Duo-Binary. However, as data rate increase, particularly into the gigabit range, these may prove inadequate because of, e.g., severe Inter-Symbol Interference (ISI), strong attenuation, data-dependent performance, and crosstalk.
Severe ISI, in particular, requires the use of specialized recovery circuits. Various types of recovery circuits are available, and are classified according to their location. Pre-Emphasis or De-Emphasis circuits may be used at the transmitter end. Forward Equalization (e.g., R-C/FFE) circuits and Decision Feedback Equalizer (DFE) circuits may be used at the receiver end.
Of these, DFE is generally regarded as the most powerful at removing Post-Cursor ISI. This is in part because DFE does not require Pre-Emphasis, which aggravates crosstalk in the channel. In addition, DFE does not add up high-frequency noise the way that, e.g., finite impulse response (FIR) filtering may do.
However, many existing DFE techniques require training. “Blind adaptive” techniques that do not require training also are known, but may be insufficiently discriminating as between valid and erroneous signals.